1. Technical Field
This disclosure relates to noise suppression and more particularly, to an apparatus and method for noise suppression by employing hysteresis.
2. Description of the Related Art
Analog circuits often include noisy signals. Noisy signals may result in bit errors when converting the analog signals to digital signals. Noise suppression can reduce noise. For example, in receiver circuits that convert (noisy) analog input signals to digital on-chip signals hysteresis is one desired means to suppress noise. In instances of slope reversal of ill terminated signal traces and extremely slow transitions (e.g., in burn-in test setups for semiconductor device tests) superimposed with random noise can cause incomplete pulses and spikes of the on-chip digital signals. This can cause malfunction of circuitry that assumes certain minimum and maximum pulse widths.
A structure of a differential amplifier-based receiver is shown in FIG. 1. A first stage 10 includes an N-channel differential pair 11 with a P-channel current mirror 13. A second stage 12 is realized by an inverter 14. One advantage of this configuration is that a switch-point is very well defined by the reference voltage VREF. The switch-point is the input voltage level (VIN) at which the output switches. For good system performance, a hysteresis of about 5-10% of the input voltage (VIN) swing is desirable. For stub series terminated logic (SSTL-2, for example), this would be about a few tens of mV's.
The prior art realization of receivers with hysteresis does not typically provide sufficient hysteresis control. The prior art provides weak controllability (i.e. achieving a small shift of the switch point based on the output state) or slow reaction time (i.e. capability to suppress fast noise spikes).
In U.S. Pat. No. 5,796,281, adding additional current to an output node of a first stage (differential amplifier) creates hysteresis. Note however, that the amount of current added is not well controlled and thus the amount of hysteresis is not well controlled. To achieve small hysteresis the transistors (for example, Q2 in U.S. Pat. No. 5,796,281) that switch the additional current have to be a small fraction of the size of main transistors of the amplifiers in U.S. Pat. No. 5,796,281. For speed purposes, however, these transistors are close to their minimum size already. Thus, it is very difficult, if not impossible, to achieve small and controlled amounts of hysteresis. Note that a hysteresis, which is too large, will also adversely affect speed. FIGS. 26.4 and 26.5 of Baker et al., "CMOS Circuit Design, Layout and Simulation," IEEE press 1998, also show circuitry for providing additional current at an output node of a first stage to attempt to control hysteresis. This circuit suffers from the same drawbacks as described above.
In other attempts to introduce controlled small amounts of hysteresis, a reference voltage is shifted based on the output state of the receiver. Although some controllability is achieved, the switching process takes too long to effectively help suppress noise spikes. It also requires two reference voltage generators, which cause additional current consumption. See e.g., U.S. Pat. No. 4,775,807.
In U.S. Pat. No. 4,745,365, the solution described consumes even more power by utilizing two receivers with offset VREF. Both receivers have to run at the same speed.
Therefore, a need exists for an apparatus for reliably controlling hysteresis for noise suppression in analog to digital conversions.